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  1. Division takes much more time compared to multiplication in hardware design (True / False). (2 points)
  2.  
  3. Any division by constant can be converted to a series of add and shifts (TRUE/FLASE). (2 points)
  4.  
  5. In Booth recoding, the longer the sequence of 1’s, the larger the saving in hardware can be achieved (TRUE/FALSE). (2 points)
  6.  
  7. Multiplication using right shift algorithm uses roughly the same amount of hardware as left shift algorithm (TRUE/FALSE). (2 points)
  1. Consider the radix 8 GSD (Generalized Sign Digit) representation of numbers using digit set [-5, 4]. Answer the following questions:
  2.  
  3. a) Represent the numbers x = 420 and y = -207 in this number system

x  =      1          -1         -3         -4

y =       0          -3         -2         1

  1.  
  2. b) Perform the addition x+y

1          -4         -5         -3

 

  1. c) Perform the following addition in the same number system.

     

    0          -4         -3         -5         4         

                1          -2         -1         -1         3

    ——————————————————-

                1          -6         -4         -6         7

                1          2          -4         2          -1

                -1         0          -1         1

    ——————————————————-

                0          2          -5         3          -1

Problem 4 – Binary Multiplication   

 

  1. a) Represent A = -30 and X = -23 as 6-bit , 2’s complement numbers.
  1. b) Compute A x X to get a 12 bit product P using the sequential right shift algorithm.

 

c) Compute A x X to get a 12 bit product P using original Booth algorithm. (8 points)

Problem 5 – Additive Multiply Modules (AMMs)

 

  1. a) Design a 4×4 AMM (Additive Multiply Module) with two 4-bit additive inputs that computes the 8-bit value p = a . x + b + y, where a, b, x and y are 4-bit unsigned numbers, using only single bit full adders and logic gates. Draw the schematic of your design and find the critical path delay for your module based on the delay of FA.
  1. Design an 8×8 multiplier using four AMMs of part a and no other components. Show all the connections along with their labels and indices on next page.

 

Note: You do not need the answer from part (a) to do this.

Problem 6 – Synthesis of Wide Multipliers

The following diagram shows a 12×4 parallel multiplier using 4×4 multipliers and 4-bit adders as only building blocks.

  1. a) Label all signals precisely on the schematic.
  1. b) Assuming each 4×4 multiplier takes 6 ns and each 4-bit adder takes 3 ns, highlight the critical path on your design and calculate the amount of the delay.

Critical path delay = 6 + 3(3) = 15 ns

  1. Pipeline the design for maximum throughput.
  2. Repeat part (c) assuming each 4×4 multiplier takes 6 ns and each 4-bit adder takes 4 ns.

Problem 7 – Unsigned Squarer Design

Design an optimum 4-bit unsigned squarer.

Note: Your design should be with the minimum amount of hardware to get full credit.

  1. multiply by 211

 

  1. multiply by 3.25
  1. Build the optimum CSA (Carry Save Adder) three to add five 16-bit unsigned numbers that are partial products of a 16×5 multiplication. Show the details of each CSA in terms of input and output width.

                                    19-4     18-3     17-2     16-1     0-15

                                                            ————————

                                                                17-2          17-1

                                                ———————————

                                                  18-3        18-2    

                                    —————————–

                                      19-4             19-3